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diff --git a/LICENCE b/LICENCE
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diff --git a/notes b/notes
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+Input power supply needs to be reasonable and we'll buck that down to 5v.
+Anything based on the MC34063 seems plausible, they're cheap and require only a
+few external components. Also there is already a schematic symbol in KiCAD.
+ is a possible datasheet for this.
+The 5v rail shall be considered the primary supply rail, we want to provide for
+the chromecast audio and also all the 3.3v logic. The logic alone totals
+almost 100mA and then we need some spare for other things, so we should assume
+we want around 750mA at 5v if we're to offer a full 500mA to the USB.
+The CCA only draws a characterised 200mA at 5v, so we could get away with 500mA
+at 5v total buck output. An MC34063 based system should be capable of up to
+1.5A though, so we can arrange for a reasonable output current.
+GIven we in theory want 750mA max output, and the peak current in step down is
+twice the desired current, we need a 1.5A to 3A capable schottky diode for the
+output and so perhaps might do.
+Working through the calculations in table 12 of the sheet above, with the
+following goal parameters:
+Vout = 5v
+Iout(max) = 1.5A
+Vripple(p-p) = 50mV
+Vin(min) = 9v
+Vsat = 1v (darlington configuration since step down)
+Vf = 600mV (From the diode above)
+Fmin = 100KHz (theoretical maximum of the device)
+Ton/Toff = (5 + 0.6) / (9 - 1 - 5) = 5.6 / 3 = 1.87
+(Ton+Toff)max = 1/100000 = 10uS
+Ton = 6.515uS
+Ct = 4.5e-5 * Ton = 293pF
+Ipk(switch) = 2*Iout(max) = 1.5A
+Rsc = 0.3 / Ipk = 0.13 ohms
+Co = (Ipk(switch) * (Ton+Toff)) / (8 * Vripple(p-p))
+ = (1.5 * 10uS) / (8 * 50mV)
+ = 0.000015 / 0.4 = 0.0000375 = 37.5 uF
+L(min) = (Vin(min) - Vsat - Vout) / Ipk(sw) * Ton(min)
+ = (9 - 1 - 5) / 1.5 * 6.515uS
+ = 2 * 6.515
+ = 13 uH
+In addition, we need to calculate the divider ratio, we want 5v out
+and the reference is 1.25v meaning we need a 1.25 : 3.75 divider
+Vout = 1.25 (1 + R2/R1)
+5v = 1.25 (1 + R2/R1)
+R2/R1 = 3
+As such, perhaps a 10K below 3 10Ks in series?
+A useful appnote sheet on this DCDC is:
+We're going to split the board into a number of 3.3v domains.
+FP_VDD - Front panel (likely 80mA to 100mA needed)
+DAC_DVDD - DAC digital power (naff all needed)
+DAC_AVDD - DAC analogue power (20mA or so needed I think)
+STM_VDD - STM32 power (a few tens of mA)
+RX_VDD - S/PDIF receiver circuitry (20mA or so needed)
+is a reasonable LDO, in SOT23-3 format it should be pretty easy to fit plenty
+of them onto the board.
+Alternatively we could use: which
+would give us the ability to perhaps control the power wells independently
+which might be fun. We could have the STM32 power up first, set up its IOs and
+then bring up each part in turn. Specifically we'd use the TPS78833 which is
+the 3.3v option.
+We need to find some suitable low-ESR (but not ultra-low ESR) surface-mount
+capacitors suitable for use for the LDOs. F920J475MPA will do at 7.4p each
+from Mouser. It's worth noting that these tants are polarised and 0805.
+The display board we're looking at from acme systems is:
+Based on datasheets I think it's around 80mA @ 3.3v It has a 10 way 0.1" pitch
+connector. The connector is not fully connected, so we can possibly put other
+stuff onto the same pin header on our board.
+3.3v 1 2
+ 3 4
+ 5 6
+SDA 7 8 SCL
+ 9 10 GND
+In theory we could put all sorts on 2-6 and 9. My gut feeling is that I'll
+put 3.3v on 2 and GND on 9, leaving 3,4,5,6 as possible other signals.
+There are no pullups on the board for the I2C, so that needs to be taken into
+account when we put the I2C bus around the board.
+We're using
+(WM8804) as the S/PDIF receiver/decoder. It only has 1 input so if we're to
+have coax *and* optical inputs then we need to work out how to arrange for
+those to be combined into the receiver. Some kind of 2-to-1 mux will be
+We're using (PCM5102A) as the
+DAC. It takes I2S in (from the S/PDIF receiver) and generates direct line level
+analogue outputs. Nice and simple to cad for.
+We're using an STM32F103CB(T6) which is the LQFP48 stm32 we used on the ekey.
+We're used to it, we know how it works, I'm confident I can lay out for it to
+run successfully (perhaps even on 2 layers) and it has enough features for what
+we need it to do. (Ditto, there's already a symbol for it in KiCAD)
+The Input (toslink / s/pdif) connector is FC684206R and is a CLIFF connector
+which incorporates the TOSLINK and S/PDIF COAX connectors.
+It's going to take a lot of work to get the footprint done properly because the
+sodding thing has awful scans as datasheets.
+The datasheet from is probably the best copy. We're going to
+need NPTH and PTH holes, some pins, some mechanical.
+The COAX pins are at the "back" of the device, one is centered the other
+offset. The centered pin is the signal, the offset is the ground for the COAX.
+Someone did a device using this which included schematics:
+In order to MUX this effectively, we need to take the COAX input and the
+TOSLINK input and be able to select between them. To do this, a quad 2-input
+NAND chip will work. A 74AC110000 from TI would be good if we can get it:
+In brief, use one as a NOT gate for SEL, feed COAX and SEL into one, giving
+nCOAX/1, feed TOSLINK and nSEL into the other, giving nTOSLINK/1. Feed nCOAX/1
+and nTOSLINK/1 into the final NAND gate, getting COAX/TOSLINK.
+Mouser cheaper than Digikey for low volume for the TI part.
+The soft-mute on the DAC is meant to be fail-safe. As such it will be pulled
+up to 3.3v by a divider on the 5v rail since that will collapse before the AVDD
+well. A diode to allow that to be grounded by the GPIO on the STM32 will then
+allow us to mute on demand. By pulling the STM32 side of that diode *down*,
+we will hold the DAC in mute until the STM32 chooses to unmute it by driving
+that GPIO pin high to halt the drain via the diode.
+See Page 30 of the PCM5102A datasheet for an example circuit.
+Also, depending on the way that GEN_FLAG is implemented, it may be worth
+directly ORing in that output into the mute line so that if the receiver says
+that there's nothing to play, we mute the DAC.
+Signals needed from the STM32 include:
+Full JTAG
+Programming serial port incl. boot pin control.
+Front panel connector (I2C)
+GPIOs to the DAC including: DEMP, FLT, FMT, XSMT-via-diode
+WM8804 needs an I2C link and a reset and config line control.
+Required pin-strapping for the WM8804 include enough that we should likely link
+all the relevant lines to the STM32 and then we can hold it in reset, set the
+pins up, release reset, and then reset those pins into high-Z and/or I2C as
+appropriate. As such, it might be best if we can have independent I2C lines to
+the front panel so that we don't confuse that panel by our WM8804 startup
+strapping since it may include SCL/SDA.
+Other component selections (passives etc)
+I have chosen 0805 for the most part here, though 0603 exist for many
+1uF Ceramic capacitor (0805) VJ0805Y105KXQTW1BC (3.3p Mouser)
+10uF Ceramic capacitor (0805) VJ0805G106KXQTW1BC (6.6p Mouser)
+100nF Ceramic capacitor (0805) VJ0805V104ZXQCW1BC (6.6p Mouser)
+10k resistor (0805) AS08J1002ET (3.9p Mouser)
diff --git a/samdac-cache.lib b/samdac-cache.lib
new file mode 100644
index 0000000..2063b3a
--- /dev/null
+++ b/samdac-cache.lib
@@ -0,0 +1,4 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#End Library
diff --git a/samdac.kicad_pcb b/samdac.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/samdac.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/ b/
new file mode 100644
index 0000000..42ddcb1
--- /dev/null
+++ b/
@@ -0,0 +1,63 @@
+update=Fri 22 Jan 2016 22:53:53 GMT
diff --git a/samdac.sch b/samdac.sch
new file mode 100644
index 0000000..27ab2df
--- /dev/null
+++ b/samdac.sch
@@ -0,0 +1,48 @@
+EESchema Schematic File Version 2
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""